One or more embodiments of the present invention pertain to methods for use in fabricating integrated circuit device structures.
Integrated circuits or devices (xe2x80x9cICsxe2x80x9d) contain an ever increasing number of devices that operate at ever increasing speeds to provide an ever increasing amount of functionality. One consequence is that transistor devices (and other structures) that form building blocks of ICs are being made smaller and smaller. In addition, in order to keep up with decreasing costs of ICs, IC manufacturers require yields to improve, even as the size of transistor devices (and other structures) goes down.
In forming transistor devices on a wafer or substrate in accordance with typical prior art IC manufacturing techniques, a sacrificial oxide layer and a nitride layer are deposited on the substrate to enable fabrication of shallow trench isolation (xe2x80x9cSTIxe2x80x9d) structures (as is well known, the sacrificial oxide layer is formed because a nitride layer does not adhere directly to the silicon substrate). Next, the STIs are formed, and the nitride layer and the sacrificial oxide layer are removed. Next, a gate oxide layer is formed on the substrate, and a polysilicon layer is formed thereon. Next, the polysilicon layer is plasma etched to define the gate (sometimes after n-doping some devices on the wafer, and p-doping other devices on the wafer) using, for example, a low selectivity-to-oxide xe2x80x9cmainxe2x80x9d etch for a majority of the thickness of the polysilicon layer (the gate oxide acts as an etch stop), and then a high selectivity-to-oxide etch for the remainder of the polysilicon layer. Next, a silicide layer (for example, a TiSix layer) that forms a portion of the source/drain is created. Next, a dielectric layer, for example, an oxide layer, is deposited on the wafer (for example, over the silicide layer). Next, source/drain contact holes are defined by a photoresist (xe2x80x9cPRxe2x80x9d) patterning process. Next, a plasma xe2x80x9ccontactxe2x80x9d etch process etches the oxide layer to form or open the contact holes.
In forming transistor devices according to the above-described prior art IC manufacturing techniques, several problems occur. A first problem in using the above-described prior art IC manufacturing techniques occurs because source/drain contacts of the transistor device are formed using a PR patterning process. Because such a PR patterning process suffers from alignment errors, the source/drain contacts may be asymmetrically located with respect to the gate electrode of the transistor device, and/or the source/drain contacts may touch the edge of the device (this may cause problems such as device leakage). To mitigate the effect of such alignment errors, design allowances must be made. Typical design allowances limit the size of the contacts, as well as distances between the source/drain contacts and the gate electrode. Hence, it is difficult to shrink the size of the transistor device.
A second problem in using the above-described prior art IC manufacturing techniques occurs because etching the dielectric layer (for example, using a plasma xe2x80x9ccontactxe2x80x9d etch process) to form a contact hole is a difficult process to control, and to control accurately.
A third problem in using the above-described prior art IC manufacturing techniques occurs because of the manner in which the source/drain are formed. As described above, a plasma xe2x80x9ccontactxe2x80x9d etch process opens source/drain contact holes, and as a result, a silicide layer is exposed to the plasma contact etch, and may be damaged. Such damage may increase contact resistance, and, together with design restrictions on the size of the contact, makes it more difficult to design low resistance contacts.
A fourth problem in using the above-described prior art IC manufacturing techniques occurs because of the need to fabricate faster and smaller devices. To do this, one might use materials other than polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d) to fabricate the gate electrode. In particular, one might use materials such as, for example, tungsten (xe2x80x9cWxe2x80x9d), silicon-germanium (xe2x80x9cSiGexe2x80x9d), and so forth. One problem with using such materials to fabricate the gate electrode in accordance with a typical prior art fabrication process is a need to develop methods to etch them.
A fifth problem in using the above-described prior art IC manufacturing techniques occurs because of limitations in current photolithography in defining dimensions less than 0.13 xcexcm. Because of these limitations, there is a need to develop structures that are used to define the width of a gate electrode. In accordance with prior art IC manufacturing techniques, structures used to define the width of the gate electrode are formed by etching PR layers laterally. This is a problem because (when such etching processes are used) the thickness of the PR layer decreases at the same time that it is trimmed laterally. As a result, the PR layer may become too thin to act reliably as a mask for etching the gate electrode.
A sixth problem in using the above-described prior art IC manufacturing techniques occurs when the gate electrode comprises a metal/polysilicon gate structure. In accordance with prior art techniques, a thickness of the polysilicon layer must be large enough to enable the polysilicon layer to provide an etch stop for an etch process that defines the metal gate. This causes a problem because it is desirable for the polysilicon layer to be thin (the thinner the better) to form a fast device. The need for the polysilicon layer to act as an etch stop inhibits a designer""s ability to make the polysilicon layer as thin as possible, and hence, impacts device speed.
A seventh problem in using the above-described prior art IC manufacturing techniques occurs when a polysilicon layer is plasma etched to define the gate. For example, when a majority of the thickness of the polysilicon layer is etched using a low selectivity-to-oxide main etch, the gate oxide may be exposed to the plasma and, thereby, suffer some damage. Further, the plasma etch process may punch through the gate oxide to fatally damage the device.
An eighth problem in using the above-described prior art IC manufacturing techniques occurs because of the manner in which the gate is formed. As was described above, a sacrificial oxide layer and a nitride layer are deposited on the substrate to enable fabrication of STI structures. Next, after the STI structures are formed, the nitride layer and the sacrificial oxide layer are removed (thereby processing the silicon substrate surface). Next, a gate oxide layer is formed. Because of this, the gate oxide layer in the device has been formed on a processed silicon surface. Such processing of the substrate may reduce the yield of the devices since the gate oxide is perhaps the most fragile component of the device.
A ninth problem in using the above-described prior art IC manufacturing techniques occurs because fabrication of p-channel CMOS devices requires etching p-doped gate electrodes, and fabrication of n-channel CMOS devices requires etching n-doped gate electrodes. However, n-doped gate electrodes etch faster than p-doped gate electrodes. This causes a problem in etching when ICs having both types of devices (known as dual gate) are fabricated on the same substrate.
A tenth problem in using the above-described prior art IC manufacturing techniques occurs because differences in sidewall profile slope result in areas of a substrate (used to fabricate the ICs) that have densely spaced devices, and areas of the substrate that have substantially less densely spaced devices. As is well known, such differences in sidewall profile slope occur because of backsputter due to etching areas surrounding the devices. For example, for sparsely spaced devices, there is more backsputter than for densely spaced devices.
In light of the above, there is a need in the art for methods that solve one or more of the above-described problems.
One or more embodiments of the present invention advantageously satisfy the above-identified need in the art, and provide one or more methods for use in fabricating integrated circuit device structures. Specifically, one embodiment of the present invention is a quasi-damascene gate, self-aligned source/drain method for forming a device on a substrate that comprises steps of: (a) forming a gate dielectric layer over the substrate; (b) forming a first gate electrode layer over the gate dielectric layer; (c) forming a contact etch stop layer over the first gate electrode layer; (d) forming a self-aligning layer over the contact etch stop layer; and (e) forming and patterning a mask over the self-aligning layer.